The present invention relates to a method and/or architecture for a high voltage tolerant circuit fabricated with a low voltage process generally and, more particularly, to an n-well bias control within the circuit that may not require high voltage transistors.
The use of low voltage technologies (i.e., 3.3 volts) for CMOS transistor circuits create problems in TTL environments. Some transistors of a low voltage circuit must provide an interface to an output of a TTL capable circuit. The TTL capable circuits may drive the interface to overvoltage (i.e., as high as 5.5 volts) conditions. Consequently, the low voltage technologies must include fabrication steps that result in some or all of the transistors being tolerant of the TTL voltage levels. Such fabrication steps add to the complexity and cost of parts fabricated by using the low voltage technologies.
Another problem created by mixing 3.3 volt MOS transistors with 5 volt TTL signals is in the basic operation of p-channel type field effect transistors (PFET). A diode formed between a p-type drain diffusion in an n-type well of the PFET must remain reverse biased for proper operation. When the interface drives a PFET drain to 5 volts, and the n-well is biased to only 3.3 volts, then the drain-to-well diode becomes forward biased. The forward biased diode creates a leakage path from the interface to a power source for the low voltage circuit.
The present invention concerns a circuit that may be configured to provide a first well bias voltage to the output buffer when the output buffer is in a first mode and to provide a second well bias voltage to the output buffer when the output buffer is in a second mode. The first well bias voltage and the second well bias voltage may be used to maintain a reverse bias in diffusion wells used for electrical isolation of transistors.
The objects, features and advantages of the present invention include providing a well bias voltage control circuit within a high voltage tolerant interface circuit that may (i) maintain low voltages across transistor thin gate oxides, (ii) present signals at the interface at reasonable drive strength levels, and/or (iii) minimize leakage currents between the interface and a supply voltage source.